* uncommented code which inserts the designName in config.mk
* removed code which inserts the designName parameter in Verilog

* removed previous code used to generate output Verilog
* removed previous code used to copy generated Verilog

* removed code which replaces `.template` in source Verilog filenames
because it seemed unncessary

because it's output filename is the same as the input filename

* added docstring to the __init__.py file
* added docstrings to the functions defined in verilog_generation module

* added commonly used Verilog functions as defs in the Mako template
* updated the source verilog code to use the new defs
* added a TODO: comment to improve this way of importing defs in the future

* uncommented code for generating `blocks/sky130hd/tempsenseInst_custom_net.txt` and `blocks/sky130hd/tempsenseInst_domain_insts.txt` files
* updated the source file path to reflect the changes in Verilog generation

* renamed all functions beginning with double _ to single _ to make them accessible using import <module_name>

* Added unit tests using pytest in test/ directory
* Used part of temp-sense-gen Verilog for unit tests
* Added tests with 6 and 8 inverters

* tests if the directory structure of the source is maintained in the output
* tests if output for files in subdirectories are generated as expected

* updated any filenames and links that have changed
* mentioned the use of Mako syntax

…module